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cy8ctst110 truetouch? single-touch touchscreen controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-46931 rev. *b revised july 28, 2008 features truetouch ? capacitive touchscreen controller ? supports single-touch touchscreen applications ? supports up to 24 x/y sensor inputs ? supports screen sizes 4.3? and below (typical) ? fast scan rates: typical 0.5 ms per sensor ? high resolution: typical 320 x 240 for 2.6? screen ? available in 32-pin qfn package ? transition to higher function multi-touch gesture device highly configurable sensing circuitry ? allows maximum design flexibility ? allows trade-off between scan time and noise performance provides maximum emi immunity ? selectable spread-spectrum clock source low power truetouch single-touch touchscreen device ? 4 ma average supply current at 8 ms report rate ? 2 ma average supply current at 16 ms report rate powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? low power at high speed ? 2.7v to 5.25v operating voltage ? industrial temperature range: ?40c to +85c flexible on-chip memory ? 8k flash program storage, 50000 erase/write cycles ? 512 bytes sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc designer?) ? truetouch touchscreen tuner ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 2.5% 24/48 mhz oscillator ? internal oscillator for watchdog and sleep programmable pin configurations ? 25 ma sink, 10 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 8 analog inputs on gpio ? configurable interrupt on all gpio additional system resources ? i 2 c? master, slave, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference logic block diagram [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 2 of 32 truetouch functional overview the truetouch family provides the fastest and most efficient way to develop and tune a capacitive touchscreen application. a truetouch device includes the configurable truetouch block, configurable analog and digital logic, and programmable inter- connect. this architecture enables the user to create flexible, customized touchscreen configur ations to match the require- ments of each individual touchscreen application. various configurations of flash program memory, sram data memory, and configurable io are included in a range of convenient pinouts. the truetouch architecture consists of four main areas: the core, the system resources, the digital system, and the truetouch analog system. configurable global bus resources allow combining all the device re sources into a complete custom touchscreen system. each cy 8ctst110 truetouch device includes four digital blocks and the truetouch controller block that provides single-touch sensing and scanning control circuitry for touchscreen applications. the cy8ctst110 is offered in a 32-pin qfn package with up to 28 general purpose io (gpio), and support of up to 24 x/y sensors. when designing touchscreen applications, refer to the um data sheet for performance requirements to meet and detailed design process explanation. the truetouch core the core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four mips 8-bit harvard architecture microprocessor. system resources provide the following additional capabilities: digital clocks to increase the flexibility of the psoc mixed-signal arrays. i2c functionality to implement an i2c master and slave. an internal voltage reference, multimaster, that provides an absolute value of 1.3v to a number of truetouch subsystems. various system resets supported by the m8c. the digital system consists of an array of digital blocks that may be configured into any number of digital peripherals. the digital blocks are connected to the gpio through a series of global buses that can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. the analog system consists of four analog psoc blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. implementation of touchscreen applications allow additional digital and analog resources to be used, depending on the touch- screen design. the digital system the digital system consists of four digital psoc blocks. each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. digital peripheral configurations include the following. pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity spi master and slave i2c slave and multi-master pseudo random sequence generators (8 to 32 bit) the digital blocks are connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow signal multiplexing and performing logic operations. this configurability frees your de signs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by truetouch device family. this allows the optimum choice of system resources for your application. family characteristics are shown in table 1 on page 4. figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect po r t 3 po r t 2 po r t 1 po r t 0 [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 3 of 32 the analog system the analog system consists of four configurable blocks that allow the creation of complex analog signal flows. implementation of touchscreen applications allow additional analog resources to be used, depending on the touchscreen design. analog peripherals are very flexible and may be customized to support specific application requirements. some of the additional truetouch analog functions for this device (most available as user modules) are: analog-to-digital converters (single or dual, with 8-bit resolution) pin-to-pin comparator single-ended comparators (up to 2) with absolute (1.3v) reference or 8-bit dac reference 1.3v reference (as a system resource) figure 2. analog system block diagram the analog multiplexer system the analog mux bus connects to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for capacitive sensing with the truetouch block comparator. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. switch control logic enables selected pins to switch dynamically under hardware control. this all ows capacitive measurement for touchscreen applications. other mu ltiplexer applications include: chip-wide mux that allows analog input from any io pin. electrical connection betwe en any io pin combinations. additional system resources system resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. additional resources include low voltage detection and power on reset. brief statements describing the merits of each system resource follow. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks may be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i2c module provides 100 and 400 khz communication over two wires. slave, master, an d multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit eli minates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system, including adcs and dacs. versatile analog multiplexer system. ac o l 1 m u x ace00 ace01 array array input configuration ase10 ase11 x x x x x an a l o g mu x bus a ll io aci0[1:0] aci1[1:0] [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 4 of 32 getting started to understand the truetouch sili con, read this data sheet and use the psoc designer? integrated development environment (ide). this data sheet is an overvi ew of the general silicon infor- mation and electrical specifications. for in depth touchscreen application information, including touchscreen specific specifica- tions, read the touchscreen us er module data sheet that is supported by this specific device. truetouch device characteristics depending on your truetouch device selected for a touchscreen application, characteristics and capabilities of each device change. ta b l e 1 lists the touchscreen sensing capabilities available for specific truetouch devices. the truetouch device covered by this data sheet is highlighted in this table. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page and click psoc (program- mable system-on-chip) to view a current list of available items. technical training modules free psoc technical training modules are available for users new to psoc. training modules cover designing, debugging, advanced analog, and general psoc related topics. go to http://www.cypress.com/training . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com , click on design support located on the left side of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they are available with a four hour guaranteed response at http://www.cypress.com/support . application notes a long list of application notes c an assist you in every aspect of your design effort. to view the psoc application notes, go to http://www.cypress.com web site and select application notes under the design resources list located in the center of the web page. application notes are sorted by date by default. development tools psoc designer is a microsoft ? windows based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp (see figure 3 on page 5). psoc designer helps the customer to select an operating configuration for the psoc, write application code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high level c language compiler developed specifically for the devices in the family. table 1. truetouch device characteristics truetouch part number sensor inputs max screen size (inches) single-touch multi-touch gesture multi-touch all-point scan speed (ms) [1] current consumption [2] flash size sram size cy8ctst110 up to 24 4.3? y n n 0.5 3 8k 512 bytes cy8ctst120 up to 44 8.4? y n n 0.5 16 16k 1k cy8ctmg110 up to 24 4.3? y y n 0.5 3 8k 512 bytes cy8ctmg120 up to 44 8.4 y y n 0.5 16 16k 1k cy8ctma120 up to 37 7.3? y y y 0.12 16 16k 1k notes 1. per sensor typical. depends on touchscr een panel. for ma120 per x/y crossing vcc = 3.3v 2. average ma supply current. based on 8 ms report rate, except for ma120. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 5 of 32 figure 3. psoc designer subsystems truetouch designer software subsystems device editor the device editor subsystem enables the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration allows changing configurations at run time. psoc designer? sets up power on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components. if the project uses more than one operating configuration, then it contains routines to switch between different sets of psoc block configurations at run time. psoc designer prints out a configuration sheet for a given project configuration for use during application programming in conjunction with the device data sheet. after the framework is generated, the user adds applicatio n-specific code to flesh out the framework. it is also possible to change the selected components and regenerate the framework. design browser the design browser enables users to select and import preconfigured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples prov ided in the tools include a 300-baud modem, lin bus master and slave, fan controller, and magnetic card reader. application editor the application editor edits c language and assembly language source code. it also assembles, compiles, links, and builds. assembler. the macro assembler allows the seamless merging of the assembly code with c code. the link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing. c language compiler. a c language compiler that supports the psoc family of devices is available. even if you have never worked in the c language before, the product quickly helps you create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read the program and read and write data memory, read and write io registers, read and write cpu r egisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. truetouch touchscreen tuner the truetouch tuner is a microsoft ? windows based graphical user interface allowing developer s to set critical parameters and observe changes to the touchscreen application in real time. optimal configuration from the tuner can be immediately applied to the truetouch user module settings. commands results psoc designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interface context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc designer [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 6 of 32 designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has severa l registers that determine its function and connectivity to other blocks, mu ltiplexers, buses and to the io pins. iterative development cycl es permit you to adapt the hardware and software. this su bstantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer integrated development environm ent (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library contains over 50 common peripherals such as adcs, dacs timers, counters, uarts, a nd other uncommon peripherals, such as dtmf generators and bi-quad analog filter sections. each user module establishes t he basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high-level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines that you can adapt as needed. the api functions are document ed in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specificatio ns. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you can pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you must also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate applicat ion? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high-level user module api functions. figure 4. user module and source code development flows the next step is to write your main program, and any sub-routines using psoc designer?s application editor subsystem. the application edit or includes a project manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional-strength ?makefile? sy stem to automatically analyze all file dependencies and run the compiler and assembler as necessary. project-level options control optimizat ion strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-va riable features, the debugger provides a large trace buffer and enables you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 7 of 32 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 5 on page 12 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. table 2. acronyms used acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor slimo slow imo smp switch mode pump sram static random access memory [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 8 of 32 pin information the cy8ctst110 truetouch device is available in a 32-pin qfn package which is listed in the following tables. every port pin (l abeled with a ?p?) is capable of digital io and connection to the common analog bus. however, vss, vdd, smp, and xres are not capable of digital io. 32-pin part pinout figure 5. cy8ctst110 32-pin sawn truetouch device a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] m, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[1] m, 12c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, 12c sda, p1[5] m, p1[3] m, 12c scl, p1[1] vss m, 12c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 9 of 32 table 3. pin definitions - cy8ctst110 32-pin (qfn) pin no. type name description digital analog 1 io i, m p0[1] analog column mux input, integrating input. 2 io m p2[7] 3 io m p2[5] 4 io m p2[3] 5 io m p2[1] 6 io m p3[3] 7 io m p3[1] 8 io m p1[7] i2c serial clock (scl). 9 io m p1[5] i2c serial data (sda). 10 io m p1[3] 11 io m p1[1] i2c serial clock (scl), issp-sclk [3] . 12 power vss ground. connect to circuit ground. 13 io m p1[0] i2c serial data (sda), issp-sdata [3] . 14 io m p1[2] 15 io m p1[4] optional external clock input (extclk). 16 io m p1[6] 17 input xres active high external reset with internal pull down. 18 io m p3[0] 19 io m p3[2] 20 io m p2[0] 21 io m p2[2] 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input. 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. bypass to ground with 0.1 uf capacitor. 29 io i, m p0[7] analog column mux input. 30 io i, m p0[5] analog column mux input. 31 io i, m p0[3] analog column mux input, integrating input. 32 power vss ground. connect to circuit ground. ep power vss exposed pad is internally connected to ground. connect to circuit ground. legend a = analog, i = input, o = output, and m = analog mux input. note 3. these are the issp pins, which are not high z at por (power on reset) [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 10 of 32 56-pin part pinout the 56-pin ssop part is for the cy8ctst110 on-chip debug (ocd) truetouch device. note this part is only used for in-circuit debugging. it is not available for production. figure 6. cy8ctst110 56-pin truetouch device table 4. pin definitions - cy8ctst110 56-pin (ssop) pin no. type pin name description digital analog 1 power vss ground. connect to circuit ground. 2 io i p0[7] analog column mux input. 3 io i p0[5] analog column mux input and column output. 4 io i p0[3] analog column mux input and column output. 5 io i p0[1] analog column mux input. 6 io p2[7] 7 io p2[5] 8 io i p2[3] direct switched capacitor block input. 9 io i p2[1] direct switched capacitor block input. 10 nc no connection. leave floating. 11 nc no connection. leave floating. 12 nc no connection. leave floating. 13 nc no connection. leave floating. 14 ocd ocde ocd even data io. 15 ocd ocdo ocd odd data output. 16 power smp switch mode pump (smp) connection to required external components. 17 power vss ground. connect to circuit ground. 18 power vss ground. connect to circuit ground. 19 io p3[3] ssop 1 56 vdd 2 ai, p0[7] 55 p0[6], ai 3 ai, p0[5] 54 p0[4], ai 4 ai, p0[3] 53 p0[2], ai 5 ai, p0[1] 52 p0[0], ai 6 p2[7] 51 p2[6] 7 p2[5] 50 p2[4] 8 p2[3] 49 p2[2] 9 p2[1] 48 p2[0] 10 nc 47 nc 11 nc 46 nc 12 nc 45 p3[2] 13 nc 44 p3[0] 14 ocde 43 cclk 15 ocdo 42 hclk 16 smp 41 xres 17 vss 40 nc 18 vss 39 nc 19 p3[3] 38 nc 20 p3[1] 37 nc 21 nc 36 nc 22 nc 35 nc 23 i2c scl, p1[7] 34 p1[6] 24 i2c sda, p1[5] 33 p1[4], extclk 25 nc 32 p1[2] 26 p1[3] 31 p1[0], i2c sda, sdata 27 sclk, i2c scl, p1[1] 30 nc 28 vss 29 nc vss [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 11 of 32 20 io p3[1] 21 nc no connection. leave floating. 22 nc no connection. leave floating. 23 io p1[7] i2c serial clock (scl). 24 io p1[5] i2c serial data (sda). 25 nc no connection. leave floating. 26 io p1[3] 27 io p1[1] crystal input (xtalin), i2c serial clock (scl), issp-sclk [3] . 28 power vss ground. connect to circuit ground. 29 nc no connection. leave floating. 30 nc no connection. leave floating. 31 io p1[0] crystal output (xtalout), i2c serial data (sda), issp-sdata [3] . 32 io p1[2] 33 io p1[4] optional external clock input (extclk). 34 io p1[6] 35 nc no connection. leave floating. 36 nc no connection. leave floating. 37 nc no connection. leave floating. 38 nc no connection. leave floating. 39 nc no connection. leave floating. 40 nc no connection. leave floating. 41 input xres active high external reset with internal pull down. 42 ocd hclk ocd high-speed clock output. 43 ocd cclk ocd cpu clock output. 44 io p3[0] 45 io p3[2] 46 nc no connection. leave floating. 47 nc no connection. leave floating. 48 io i p2[0] 49 io i p2[2] 50 io p2[4] 51 io p2[6] 52 io i p0[0] analog column mux input. 53 io i p0[2] analog column mux input and column output. 54 io i p0[4] analog column mux input and column output. 55 io i p0[6] analog column mux input. 56 power vdd supply voltage. bypass with 0.1 uf capacitor to ground. legend : a = analog, i = input, o = output, and ocd = on-chip debug. table 4. pin definitions - cy8ctst110 56-pin (ssop) (continued) pin no. type pin name description digital analog [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 12 of 32 electrical specifications this section presents the dc and ac electr ical specifications of the cy8ctst110 tr uetouch device. for up to date electrical specifications, visit the web site http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c as specified, except where noted. refer table 19 on page 20 for the electrical specifications on t he internal main oscillator (imo) using slimo mode. ta b l e 5 lists the units of measure t hat are used in this section. table 5. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 figure 7. voltage versus cpu frequency figure 8. imo frequency trim options [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 13 of 32 absolute maximum ratings operating temperature table 6. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 o c higher storage temperatures reduce data retention time. recom- mended storage temperature is +25 o c 25 o c. extended duration storage temperatures above 65 o c degrade reliability. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage [4] 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 7. operating temperature symbol description min typ max units notes t a ambient temperature [5 ] -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see table 34 on page 29. the user must limit the power consumption to comply with this requirement. notes 4. see the user module data sheet for touchscreen application related esd testing. 5. see the user module data sheet for touchscreen application related temperature testing [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 14 of 32 dc electrical characteristics the below electrical characteristics are for proper cpu core and io operation. for capacitive touchscreen electrical characteri stics, refer to the touchscreen user module data sheet. dc chip-level specifications ta b l e 8 lists the guaranteed maximum and minimu m specifications for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.7v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 8. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 2.40 ? 5.25 v see table 17 on page 18. i dd supply current, imo = 24 mhz ? 3 4 ma conditions are vdd = 5.0v, t a = 25 o c, cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current, imo = 6 mhz using slimo mode. ? 1.2 2 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i dd27 supply current, imo = 6 mhz using slimo mode. ? 1.1 1.5 ma conditions are vdd = 2.55v, t a = 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4. a vdd = 2.55v, 0 o c t a 40 o c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a vdd = 3.3v, -40 o c t a 85 o c. v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate vdd. vdd = 3.0v to 5.25v. v ref27 reference voltage (bandgap) 1.16 1.30 1.33 v trimmed for appropriate vdd. vdd = 2.4v to 3.0v. agnd analog ground v ref - 0.003 v ref v ref + 0.003 v [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 15 of 32 dc general purpose io specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c. these are for design guidance only. table 9. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. table 10. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 0.4 ? ? v ioh = 2.5 ma (6.25 typ), vdd = 2.4 to 3.0v (16 ma maximum, 50 ma typ combined ioh budget). v ol low output level ? ? 0.75 v iol = 10 ma, vdd = 2.4 to 3.0v (90 ma maximum combined iol budget). v il input low level ? ? 0.75 v vdd = 2.4 to 3.0. v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0. v h input hysteresis ? 90 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 16 of 32 dc operational amplifier specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 11. 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa [6] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0.0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 12. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa [6 ] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 13. 2.7v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa [6 ] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a note 6. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1 to 7 for the lowest leakage of 200 na. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 17 of 32 dc low power comparator specifications ta b l e 1 4 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c. these are for design guidance only. dc analog mux bus specifications ta b l e 1 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. dc idac resolution ta b l e 1 6 lists idac typical resolution. typical parameters apply to 5v at 25 c. these are for design guidance only. table 14. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 15. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 800 w w vdd 2.7v 2.4v vdd 2.7v r vdd resistance of initialization switch to vdd ? ? 800 w table 16. dc idac resolution symbol description min typ max units notes i dac current output of 1 lsb (1x setting) - 90 - na [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 18 of 32 dc por and lvd specifications ta b l e 1 7 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 17. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [7] 2.99 [8] 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62 [9] 3.09 3.16 3.32 [10 ] 4.74 4.83 4.92 5.12 v v v v v v v v notes 7. always greater than 50 mv above v ppor (porlev = 00) for falling supply. 8. always greater than 50 mv above v ppor (porlev = 01) for falling supply. 9. always greater than 50 mv above v lvd0. 10. always greater than 50 mv above v lvd3. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 19 of 32 dc programming specifications ta b l e 1 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 18. dc programming specifications symbol description min typ max units notes vdd iwrit e supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enp b flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [11, 11] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years note 11. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperatur e sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 20 of 32 ac electrical characteristics ac chip level specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 19. 5v and 3.3v ac chip level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 [ 12, 13, 14] mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 8 on page 12. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 [12, 13, 14 ] mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 8 on page 12. slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 [ 12, 13], mhz 24 mhz only for slimo mode = 0. f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 [13, 14] mhz f blk5 digital psoc block frequency 0 (5v nominal) 0 48 49.2 [12, 13, 15] mhz refer to the ac digital block specifications. f blk33 digital psoc block frequency (3.3v nominal) 0 24 24.6 [13, 15] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz jitter32k 32 khz rms period jitter ? 100 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [12, 14 ] mhz trimmed. using factory trim values. jitter24m1 24 mhz peak-to-peak period jitter (imo) ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s notes 12. 4.75v < vdd < 5.25v. 13. accuracy derived from internal main oscillator with appropriate trim for vdd range. 14. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-ra nge operation? for information on trimming for operation at 3.3v. 15. see the individual user module data sheets for information on maximum frequencies for user modules. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 21 of 32 figure 8. 24 mhz period jitter (imo) timing diagram figure 9. 32 khz period jitter (ilo) timing diagram ac general purpose io specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 20. 2.7v ac chip-level specifications symbol description min typ max units notes f imo12 internal main oscillator frequency for 12 mhz 11.5 12 0 12.7 [16, 17, 18] mhz trimmed for 2.7v operation using factory trim values. see figure 8 on page 12. slimo mode = 1. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 [ 16, 17, 18] mhz trimmed for 2.7v operation using factory trim values. see figure 8 on page 12. slimo mode = 1. f cpu1 cpu frequency (2.7v nominal) 0.093 3 3.15 [16, 17] mhz 24 mhz only for slimo mode = 0. f blk27 digital psoc block frequency (2.7v nominal) 0 12 12.5 [16, 17, 18 ] mhz refer to the ac digital block specifications. f 32k1 internal low speed oscillator frequency 8 32 96 khz jitter32k 32 khz rms period jitter ? 150 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s jitter24m1 f 24m jitter32k f 32k1 table 21. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns vdd = 3 to 5.25v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns vdd = 3 to 5.25v, 10% to 90% notes 16. 2.4v < vdd < 3.0v. 17. accuracy derived from imo with appropriate trim for vdd range. 18. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range op eration? for information on maximum frequency. for user modules [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 22 of 32 figure 10. gpio timing diagram ac operational amplifier specifications ta b l e 2 3 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. ac low power comparator specifications ta b l e 2 4 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c. these are for design guidance only. ac analog mux bus specifications ta b l e 2 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 22. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% to 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 23. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv overdrive 100 200 ns ns vdd 3.0v. 2.4v < vcc < 3.0v. table 24. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 25. ac analog mux bus specifications symbol description min typ max units notes f sw switch rate ? ? 3.17 mhz [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 23 of 32 ac digital block specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 26. 5v and 3.3v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 mhz 4.75v < vdd < 5.25v. maximum block clocking frequency (< 4.75v) 24.6 mhz 3.0v < vdd < 4.75v. timer capture pulse width 50 [19] ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with or without capture ? ? 24.6 mhz counter enable pulse width 50 ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 ? ? ns disable mode 50 ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 50 ? ? ns transmitter maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. receiver maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. note 19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 24 of 32 ac external clock specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 27. 2.7v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency 12.7 mhz 2.4v < vdd < 3.0v. timer capture pulse width 100 [20 ] ? ? ns maximum frequency, with or without capture ? ? 12.7 mhz counter enable pulse width 100 ? ? ns maximum frequency, no enable input ? ? 12.7 mhz maximum frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns maximum frequency ? ? 12.7 mhz crcprs (prs mode) maximum input clock frequency ? ? 12.7 mhz crcprs (crc mode) maximum input clock frequency ? ? 12.7 mhz spim maximum input clock frequency ? ? 6.35 mhz maximum data rate at 3.17 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 100 ? ? ns transmitter maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. table 28. 5v ac external clock specifications symbol description min typ max units f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s note 20. 100 ns minimum input pulse width is based on the inpu t synchronizers running at 12 mhz (84 ns nominal period). [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 25 of 32 table 29. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 30. 2.7v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ?3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power up imo to switch 150 ? ? s [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 26 of 32 ac programming specifications ta b l e 3 1 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. ac i 2 c specifications the following tables list the guaranteed maximum and minimum sp ecifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 31. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 15 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns 3.6 < vdd t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0 table 32. ac characteristics of the i 2 c sda and scl pins for vdd 3.0v symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ? 100 [21] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns note 21. a fast-mode i2c-bus device may be used in a sta ndard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this is automatically the case if the device does not stretch the low peri od of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 27 of 32 figure 11. definition for timing for fast/standard mode on the i 2 c bus table 33. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 ??khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c setup time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ???ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 28 of 32 packaging information this section shows the packaging specificat ions for the cy8ctst110 truetouch device along with the thermal impedances for each package. it is important to note that emulation tools may require a lar ger area on the target pcb than th e chip?s footprint. for a detai led description of the emulatio n tools? dimensions, refe r to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . for information on the preferred dimensions for mount ing qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . figure 12. 32-pin sawn qfn package 001-30999 *a [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 29 of 32 figure 13. 56-pin (300-mil) ssop thermal impedances solder reflow peak temperature ta b l e 3 5 illustrates the minimum solder reflow peak temperature to achieve good solderability. 51-85062 *c table 34. thermal impedances per package package typical ja [22] typical jc 32 qfn [23] 5x5 mm 0.93 max 22 o c/w 12 o c/w table 35. solder reflow peak temperature package minimum peak temperature [24] maximum peak temperature 32 qfn 240 o c 260 o c notes 22. t j = t a + power x ja. 23. to achieve the thermal impedance specified for the qfn package , the center thermal pad must be soldered to the pcb ground pl ane. 24. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 30 of 32 development tool selection software psoc designer at the core of the psoc development software suite is psoc designer. used by thousands of psoc developers, this robust software is facilitating psoc designs for half a decade. psoc designer is available free of charge at http://www.cypress.com under design resources > software and drivers. psoc programmer psoc programmer is flexible enough to be used on the bench in development and is also suitable for factory programming. psoc programmer works either as a standalone programming appli- cation or operates directly from psoc designer or psoc express. psoc programmer softwa re is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress. com/psocprogrammer . hi-tech c lite compiler hi-tech c lite is an ansi c compiler optimized for psoc to deliver dense, efficient executable code for a smaller-than-ever footprint. hi-tech c lite is available for download at http://www.cypress.htsoft.com. to install the hi-tech lite version, download the complier ins tallation file from hi-tech and choose the lite option when prompted for a registration key. the lite version can be upgraded to the 45-day full featured evaluation version or the pro version at any time, however the pro version can only be enabled with a purchased registration key. hi-tech c pro compiler hi-tech c pro is an optional upgrade to psoc designer that offers all the benefits of hi-tech c lite with additional features. hi-tech c pro is available for purchase either at the cypress online store or at http://www.cypress.htsoft.com. hi-tech c pro is recommended for touchscre en applications using the multi-touch all-point cy8ctma120 device. cy3202-c imagecraft c compiler cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it is available at the cypress online store. at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click psoc (programmable system-on-chip) to view a current list of available items. evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices through the miniprog1 programming unit. the miniprog is a small, compact prototyping pr ogrammer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note cy3207issp needs spec ial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable [+] feedback
cy8ctst110 document number: 001-46931 rev. *b page 31 of 32 accessories (emulation and programming) third party tools several tools are specially designed by the following third party vendors to accompany psoc devices during development and production. specific details of each of these tools are found at http://www.cypress.com under design resources > evaluation boards. build a psoc emulator into your board for details on emulating the circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, see application note an2323 ?debugging - build a psoc emulator into your board?. ordering information ordering code definitions package ordering code flash (bytes) sram (bytes) single touch enabled multi-touch gesture enabled multi-touch all-point enabled x/y sensor inputs 32-pin (5x5 mm 0.93 max) sawn qfn cy8ctst110-32ltxi 8k 512 y n n up to 24 32-pin (5x5 mm 0.93 max) sawn qfn (tape and reel) cy8ctst110-32ltxit 8k 512 y n n up to 24 56-pin ocd ssop CY8CTST110-00PVXI 8k 512 y n n up to 24 cy 8 c tst xxx-32xx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx = qfn pb-free ax = tqfp pb-free pin count: 32-pin part number family code: tst = touc hscreen single-touch device technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress [+] feedback
document number: 001-46931 rev. *b revised july 28, 2008 page 32 of 32 truetouch?, psoc designer?, programmable system-on-chip?, and psoc express? are trademarks and psoc? is a registered trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c stan dard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8ctst110 ? cypress semiconductor corporation, 2008. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cente rs, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy8ctst110 truetouch? single-touch touchscreen controller document number: 001-46931 revision ecn orig. of change submission date description of change ** 2518134 dso/aesa 06/18/08 new data sheet *a 2523303 dso/pyrs 06/30/08 updated x/y sensor inputs to 24 and supported screen sizes to 4.6? and below changed operating voltage range to 2.7v to 5.25v. *b 2549257 yom/pyrs 08/06/08 added other sections based on psoc data sheets. [+] feedback

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